1. Field of the Invention
The present invention relates generally to phase locked loops, and more particularly to a phase locked loop topology with an adaptive loop filter for improved performance.
2. Description of the Related Art
A conventional phase locked loop (PLL) includes a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The loop filter normally includes a resistor in series with a capacitor. The loop gain and damping ratio typically characterize PLL performance. For a conventional PLL, the charge pump current, the VCO gain and the loop filter resistance are fixed so that it has a fixed damping ratio and a fixed loop gain.
The loop gain of the PLL should be set as close as possible to its operating frequency in order to minimize jitter of the PLL. The loop gain, however, is affected by many factors, such as, for example, process technology factors, voltage and temperature variations, and noisy environments. Conventional PLLs, therefore, have relatively narrow operating frequency range and poor jitter performance.
Existing solutions have proposed methods to make the damping ratio and the tracking bandwidth constant, where the tracking bandwidth is the ratio of loop bandwidth to PLL operating frequency. In one method, the loop filter resistor is implemented by an amplifier and set to be inversely proportional to the square root of charge pump current. Thus, the VCO frequency and the PLL loop bandwidth are also set to be proportional to the square root of charge pump current so that the ratio of loop bandwidth and PLL operating frequency is constant.